Embedded & EdgeSelected work

Embedded, FPGA & Board-Level Systems

Board-level engineering — Verilog on the Basys 3, bare-metal ATmega2560 work, a custom PCB with production Gerbers, and CMOS VLSI design.

Role — Design, firmware, and verification across the listed projects

Verilog / Artix-7Embedded C/C++ATmega2560PCB design (EAGLE/KiCad)SPICE

FPGA portfolio (Basys 3)ATmega2560 projects + PCB

Problem: AI systems eventually meet a voltage rail. This body of work is about being competent at the layer where software constraints become physical ones.
System type: Embedded / board-level systems portfolio
Why it matters: Physical-AI ambitions without hardware literacy produce systems that can't be debugged below the API. This layer keeps the rest of the stack honest.
Team context: Individual coursework and personal projects across the computer-engineering curriculum and three faculty research labs.

Block diagram (schematic placeholder — add board photos and scope traces).

Overview

A collection entry for the hardware layer under the AI stack: six Verilog systems on the Digilent Basys 3 (soft-core CPU, PicoBlaze + OLED, PS/2-to-UART), six ATmega2560 projects including a custom Arduino-Mega-class PCB with production Gerbers and a bare-metal 40 kHz ADC sampler, transistor-level CMOS designs in 0.6 µm SCMOS, and a self-balancing robot prototype running PID control with a custom integration PCB in progress. This is why the deployment work treats latency, timing, and power as real numbers instead of abstractions.

System architecture

Per project: sensors and IO into a microcontroller or FPGA, firmware or HDL in the middle, actuation and bench validation on the other side — documented per repository.

Sensors / IO

Microcontroller / FPGA

Firmware & HDL

Actuation

Bench validation

Sensors / IO

Microcontroller / FPGA

Firmware & HDL

Actuation

Bench validation

Contributions

Six self-contained Verilog systems on the Basys 3 (Artix-7): PicoBlaze + PmodOLED, XADC-to-Arduino SPI bridge, PS/2-keyboard-to-UART stack, soft-core CPU, FSMs, LCD driver.
Six ATmega2560 projects including a custom Arduino-Mega-class PCB with production Gerbers, a bare-metal 40 kHz ADC sampler, and a hand-built IR link-layer protocol.
Transistor-level CMOS design in 0.6 µm SCMOS: 8-bit ALU, R-2R DAC + flash ADC, transmission-gate MUX, full static-CMOS gate library.
Self-balancing robot prototype: PID stabilization, with a custom PCB (upgraded MCU, onboard drivers, integrated IMU) in design.

Evidence & evaluation

Evidence

Open-source repositories

attached

Three documented repos: FPGA portfolio, ATmega2560 projects, CMOS VLSI designs.

Bench test results

pending

Scope traces, validation runs, or demo clips for the strongest 1–2 pieces.

Metrics

Timing / power figures

Not yet measured

Only the ones actually measured on the bench.

Limitations

This is a collection entry — its credibility improves sharply once one project is documented end-to-end with bench evidence.

Lessons & tradeoffs

Hardware debugging builds the habit that carries into ML systems work: distrust the layer you can't observe.
[Add one concrete bench story.]to fill